1. Field of the Invention
The present invention relates to a semiconductor memory having a memory cell including a ferroelectric capacitor, and a method of controlling the semiconductor memory.
2. Description of the Related Art
Conventionally, a ferroelectric memory (semiconductor memory) which has a memory cell including a ferroelectric capacitor and stores data in accordance with the polarization direction of the ferroelectric capacitor is known. Known memory cells of this ferroelectric memory are 2T2C in which one memory cell is made up of two selection transistors and two ferroelectric capacitors, and 1T1C in which one memory cell is made up of one selection transistor and one ferroelectric capacitor.
FIG. 4 is a view showing an outline of the arrangement of a conventional 1T1C memory cell including a ferroelectric capacitor. As shown in FIG. 4, this memory cell M includes one ferroelectric capacitor C and one transistor Tr. One terminal of the ferroelectric capacitor C is connected to a bit line BL via the transistor Tr. The other terminal of this ferroelectric capacitor C is connected to a plate line PL. The bit line BL is connected to a sense amplifier 70. This bit line BL is precharged or its potential difference is amplified by activation by the sense amplifier 70. The gate terminal of the transistor Tr is connected to a word line WL, and the transistor Tr is turned on and off by controlling the signal level of this word line WL. A boosting circuit 71 is connected to the word line WL and boosts this word line WL. A plate line driver 72 is connected to the plate line PL and applies an arbitrary voltage to this plate line PL.
Referring to FIG. 4, the transistor Tr functions as a switching element for separating the bit line BL and ferroelectric capacitor C. For example, to read out data from this memory cell M, the transistor Tr is turned on to open its switching gate to connect one terminal of the ferroelectric capacitor C to the bit line BL. Then, the plate line driver 72 applies a predetermined voltage to the plate line PL, thereby applying this predetermined voltage to the other terminal of the ferroelectric capacitor C. In this manner, electric charge is output from the ferroelectric capacitor C to the bit line BL, thereby reading out the data.
To write “1” data in the memory cell M, the transistor Tr is turned on to apply a power supply voltage, which is precharged to the bit line BL, to one terminal of the ferroelectric capacitor C connected to this bit line BL. The plate line driver 72 applies 0 V to the plate line PL. Accordingly, the “1” data is written in the memory cell M. In this case, to reduce the ON resistance of the transistor Tr, the applied voltage to the gate terminal of this transistor Tr must be boosted to a voltage value (e.g., 6 to 7 V if the power supply voltage is 5 V) larger than the value of the power supply voltage described above. That is, the boosting circuit 71 boosts the value of the voltage to be applied to the word line WL so that this voltage value is larger than that of the power supply voltage precharged to the bit line BL. Consequently, the ON resistance of the transistor Tr can be reduced, and a voltage close to the power supply voltage can be applied to one terminal (on the side of the bit line BL) of the ferroelectric capacitor C. This allows the ferroelectric capacitor C to be reliably polarized.
Unfortunately, the above-mentioned boosting circuit requires a peripheral circuit for controlling the boosting timing, and this complicates the circuit configuration.
Also, it is increasingly demanded to further simplify the circuit configuration by omitting the plate line driver for applying a voltage to the plate line as described above.